The invention relates to a process for, lanarizing dielectric layers in at multi-level thin film structures and the equipment that accomplishes the same.
Thin film interconnect has been the standard for high performance multi-chip module (MCM) packaging. As a chip IO (input-output) density in an MCM module increases, the layers of thin films to interconnect among the chips and those between chip IO and peripherals increase as well. Due to metal loading distribution in wiring design, the top surface topography of thin films increases as the number of layers increases. For a typical one plane pair (x and y wiring) with power and ground mesh design (6 levels thin film) the average thin film thickness is in the range of 50 microns (approx. 2 mils). The top surface topography in such a thin film structure can vary as much as 15-20 microns (xcexcm). This is close to 40% surface topography variation. To date this level of surface topography is acceptable for MCM C4 (controlled-collapse-chipconnection) joining at 4 on 9 mil pitch. However, as the C4 pitches approach 6, 5, 4, 3 and 2 mils in the future and when more than one plane pair of thin films are required for chip interconnect, the surface topography needs to be minimized reaching to 5 xcexcm or less eventually. This requires that top surface be planarized by some suitable technique. The most straight forward approach for such planarization is to use top surface polish after each layer of dielectric coating is built on metal level. However, polishing process is expensive. In addition, polishing is difficult to extend to large format (e.g., greater than 300 mm dia.) thin film processing because the large format thin film processing carrier itself has surface variation as well as rigidity flexing, which could reach 25xcexcm or more. These factors make dielectric polish difficult to accomplish in a large size scale.
U.S. Pat. No. 5,336,353 describes methods for laminating multiple layers of printed circuit board (PCB). Multilayer PCB is an entirely different technology from multilayer thin film in accordance with the invention. Thin film packaging is used for fine pitch, high density MCM packaging with Cu polyimide construction. PCB is low density using pre-preg epoxy resin. The two technologies have different application ranges and process methods. Moreover a large (greater than 25 xcexcm) surface non planarity is observed in a PCB structure.
U.S. Pat. No. 5,633,072 discloses adhesion and void filling in a PCB process. PCB lamination and gap filling are for systems with low wiring density of over 50 xcexcm wide lines and are operated at low temperature of less than 100xc2x0 C. but high pressure of more than 2000 psi due to the large pre-preg grain in the material used. The present invention is for Cu/polyimide thin film which requires low pressure of less than 150 psi and high temperature of higher than 350xc2x0 C. due to the fine line pitch of 10 xcexcm -50 xcexcm and stable material (450xc2x0 C.).
U.S. Pat. No. 5,043,221 describes a material invention and its application to PCB. Materials used in PCB process have different properties and requirements than those used for thin film process, as the two technologies differ in processing condition and sequence.
U.S. Pat. No. 4,894,271 describes a method for PCB manufacturing. The materials used and the process conditions described in this patent are not applicable to the invention, because the invention is directed to thin film interconnect lamination and planarization at the scale of less than 15xcexcm topography by 10xcexcm wiring density which is not achievable by low density PCB technology.
U.S. Pat. No. 5,672,226 describes a method and structure in PCB processing. The material used and the process condition in this patent are not compatible with thin film process which uses Cu-polyimide construction that the invention is based on.
U.S. Pat. No. 5,679,444 describes a method for multilayer PCB construction. The process described can enhance PCB wireability by stacking multiple PCB sheets together with adhesives. PCB technology is a low density wiring technology, while the invention is directed to multilayer thin film process and planarization.
U.S. Pat. No. 5,741,575 describes an adhesive used for PCB layers adhesion. PCB processes at 200xc2x0 C. and below. The material used for PCB is not relevant to the invention, because the temperature of thin film process reaches up to 400xc2x0 C. and only polyimide material and adhesive work at such high temperature.
U.S. Pat. No. 5,637,382 describes a method of forming a free standing, flexible Cu-polyimide-Cu composite in thickness of 10 xcexcm or less. While the materials used in this patent and id their scale are similar to those used in the invention, this patent relates to the making of the flexible composite and the circuitry made by said composite. The invention, however, is directed to thin film circuitry with multiple layers of Cu-polyimide stacks and the method of planarizing the surface topography of such stacking.
Therefore, none of the cited patents address the top surface planarity of thin film module covered by this invention.
It is an object of the present invention to provide a method for planarizing the dielectric layers in a multi-level thin film structure. The method in accordance with the invention is extendable to large format processing.